Define Sap-1 Architecture with figure.

The sap-1 is the simple configuration for understanding the model and functionality of basic microprocessor. The Sap-1 consists of:

·         Program Counter(PC): : PC is the program counter that holds the address of the next instruction to be fetched. It initializes from 0000H to 1111H during the execution. It is implemented in ‘pc.v’ file.

·         MAR:  MAR is the memory address register that stores the complete format of the address send by the program counter. It stores the final address of the memory word that needs some computations.

·         RAM: The sap-1 contains the 16 bytes of memory space to hold the data and instruction which are currently in use. They are synchronous which means that the data is available to other sectors as soon as the clock signal is applied and the memory address is valid.

·         IR: The IR is the Instruction Register that holds the complete format of the Instruction that is to be executed.

·         Control Sequence: It provides necessary timing signals like T₀, T₁, T₂, …..and control signals  providing the direction for executing the program. They are implemented in ‘cu.v’ file.

·         Accumulator: The result of all the mathematical operations is stored in accumulator. It is one of the operand of ADD, OUT, SUB instruction. It is also known as processor register. It is implemented in ‘accumulator.v’ file.

·         ALU: The ALU of sap-1 performs the basic addition and subtraction. It is based on 2’s compliment format.

·         Register B:  It is the temporary register used to hold the other operand which is necessary for mathematical calculations.

·         Output register: It holds the value of operand given by OUT instruction.

Binary display: It displays the content of the output register with the use of 8 LEDs in row.