Arithmetic
logic shift unit is a digital circuit that performs arithmetic calculations,
logical manipulation and shift operation. It is often abbreviated as ALU. The
above figure shows the one stage of arithmetic logic shift unit.
The block
diagram of ALU includes one stage of arithmetic circuit, one stage of logic
circuit and one 4*1 multiplexer. The subscript i designates a typical stage.
Inputs Ai and Bi are applied to both the arithmetic and logic units. A
particular microoperation is selected with inputs S1 and S0. A 4*1 mux selects
the final output. The two inputs of the mux is received from the output of the
arithmetic circuit and logic circuit. The other two is Ai-1 for the
shift-right operation and Ai+1 for the shift left operation. The
circuit is repeated n times for n-bit ALU. The output carry Ci+1 is
connected to the input carry Cin. In every stage the circuit
specifies 8 arithmetic operations, 4 logical operations and 2 shift operations,
where each operation is selected by the five variables S3, S2,
S1, S0 and Cin.
The operations
of ALU can be summarized in table below:
Operation
select
|
operation
|
Function
|
||||
S3
|
S2
|
S1
|
S0
|
Cin
|
||
0
|
0
|
0
|
0
|
0
|
F=A
|
Transfer A
|
0
|
0
|
0
|
0
|
1
|
F=A+1
|
Increment A
|
0
|
0
|
0
|
1
|
0
|
F=A+B
|
Addition
|
0
|
0
|
0
|
1
|
1
|
F=A+B+1
|
Add with carry
|
0
|
0
|
1
|
0
|
0
|
F=A+
|
Subtract with borrow
|
0
|
0
|
1
|
0
|
1
|
F= A+
+1
|
Subtraction
|
0
|
0
|
1
|
1
|
0
|
F=A-1
|
Decrement A
|
0
|
0
|
1
|
1
|
1
|
F=A
|
Transfer A
|
0
|
1
|
0
|
0
|
╳
|
F=A˄B
|
AND
|
0
|
1
|
0
|
1
|
╳
|
F=A˅B
|
OR
|
0
|
1
|
1
|
0
|
╳
|
F=A⊕B
|
XOR
|
0
|
1
|
1
|
1
|
╳
|
F=
|
Compliment A
|
1
|
0
|
╳
|
╳
|
╳
|
F=shr A
|
Shift right A into F
|
1
|
1
|
╳
|
╳
|
╳
|
F= shl A
|
Shift left A into F
|
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